AM substrates have been widely used for AM type display devices, such as liquid crystal display devices and EL (electroluminescence) display devices. A known AM type liquid crystal display device using such an AM substrate includes a plurality of scanning signal lines formed on the substrate, a plurality of data signal lines crossing the scanning signal lines, thin-film transistors (hereinafter, referred to also as “TFTs”) located at the intersections of the above-mentioned signal lines, and other elements. An image signal is transmitted to each of pixel portions of the AM type liquid crystal display device by the switching function of the associated TFTs. Furthermore, the pixel portion may be provided with a storage capacitor element (see, for example, Patent Document 1).
Such a storage capacitor element prevents self-discharge of a liquid crystal layer during a period during which a TFT is in the off state or degradation of the image signal quality due to the off-state current of the TFT and is used not only for storage of the image signal during the period during which the TFT is in the off state but also as a path through which various modification signals are applied to the storage capacitor element to drive liquid crystal. A liquid crystal display device including a storage capacitor element can achieve low power consumption and high image quality.
An example of the known AM substrate configuration will be described hereinafter with reference to the drawings. FIG. 24 is a schematic plan view illustrating the configuration of a portion of an AM substrate corresponding to a pixel including a storage capacitor element. The AM substrate is used for a known AM type liquid crystal display device. FIG. 25 is a schematic cross-sectional view illustrating the cross section of the AM substrate taken along the line A-A′ in FIG. 24.
As illustrated in FIGS. 24 and 25, the AM substrate is provided with a plurality of pixel electrodes 51 arranged in a matrix form, scanning signal lines 52 for supplying scanning signals, and data signal lines 53 for supplying data signals. The data signal lines 53 extend along the lateral edges of the pixel electrodes 51, and the scanning signal lines 52 cross the data signal lines 53. TFTs 54 are located, as switching elements connected to the pixel electrodes 51, at the intersections of the scanning signal lines 52 and the data signal lines 53. Each scanning signal line 52 is connected to gate electrodes 62 of the associated TFTs 54, and the drive of each TFT 54 is controlled by a scanning signal fed to the associated gate electrode 62. Each data signal line 53 is connected to source electrodes 66a of the associated TFTs 54, and a data signal is fed to the source electrode 66a of the associated TFT 54. Furthermore, a drain electrode 66b is connected through a connection electrode 55 to one of electrodes (an upper storage capacitor electrode 55a) of a storage capacitor element, and the electrode of the storage capacitor element is further connected via an associated contact hole 56 formed in an interlayer insulating film 68 to the associated pixel electrode 51. A storage capacitor (common) line 57 is formed on a transparent insulating substrate (insulating substrate) 61, and the storage capacitor (common) line 57 functions as the other electrode (lower storage capacitor electrode) of the storage capacitor element.
As illustrated in FIG. 25, the gate electrode 62 is formed on the transparent insulating substrate (insulating substrate) 61 made of glass, plastic, or any other material so as to be connected to the associated scanning signal line 52. The scanning signal line 52 and the gate electrode 62 are formed of a metal film made of titanium, chromium, aluminum, molybdenum, or any other metal, an alloy of these metals, or a layered film of these metals. The storage capacitor (common) line 57 functioning as the other electrode (lower storage capacitor electrode) of the storage capacitor element is formed of the same material as the scanning signal line 52 and the gate electrode 62. A gate insulating film 63 covering the storage capacitor (common) line 57, the scanning signal line 52 and the gate electrode 62 is formed of an insulating film made of silicon nitride, silicon oxide, or any other material. A high-resistance semiconductor layer 64 made of amorphous silicon, polysilicon or any other material and a low-resistance semiconductor layer made of n+ amorphous silicon further doped with impurities, such as phosphorus, are formed on the gate insulating film 63 to overlap the gate electrode 62. The low-resistance semiconductor layer is changed into a source electrode 66a and a drain electrode 66b. 
Each data signal line 53 is formed so as to be connected to the associated source electrodes 66a. Furthermore, the connection electrode 55 is formed so as to be connected to the associated drain electrode 66b and extends continuously with one of the electrodes of the storage capacitor element, i.e., the upper storage capacitor electrode 55a. The upper storage capacitor electrode 55a is connected via the contact hole 56 to the pixel electrode 51. The data signal line 53, the connection electrode 55 and the upper storage capacitor electrode 55a are formed of the same material, such as a metal film made of titanium, chromium, aluminum, molybdenum, or any other metal, an alloy of these metals, or a layered film of these metals.
The pixel electrode 51 is formed of a transparent conductive film made of, for example, indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide, or tin oxide. The contact hole 56 passes through the interlayer insulating film 68 covering the TFT 54, the scanning signal line 52, the date signal line 53, and the connection electrode 55. As a material of the interlayer insulating film 68, use is made of, for example, an acrylic resin, silicon nitride, silicon oxide, or any other material. An AM substrate configured as illustrated in FIGS. 24 and 25 is disclosed, for example, in Patent Document 2.
For an AM substrate of such a configuration, in order to simplify a fabrication process and reduce the production cost, the storage capacitor (common) line (lower storage capacitor electrode) 57 is formed in the same process step as the scanning signal line 52, and the upper storage capacitor electrode 55a is formed in the same process step as the data signal line 53 and the connection electrode 55. Furthermore, in a case where, as illustrated in FIG. 25, the pixel electrode 51 covers the interlayer insulating film 68, this allows the pixel electrode 51 to overlap the signal lines 52 and 53. This overlapping increases the aperture ratio of a pixel and further has the effect of shielding electric fields from the signal lines 52 and 53 to the pixel electrode 51. In the above-mentioned case, the contact hole 56 is formed in a part of the interlayer insulating film 68 on a pattern forming the storage capacitor (common) line 57 or a pattern forming the scanning signal line 52. This provides connection between the pixel electrode 51 and the upper storage capacitor electrode 55a, and the upper storage capacitor electrode 55a is connected through the connection electrode 55 to the drain electrode 66b, thereby providing connection between the pixel electrode 51 and the drain electrode 66b. The location at which the contact hole 56 is formed is not limited within a region of the interlayer insulating film 68 located on the upper storage capacitor electrode 55a and may be within a region thereof located on the connection electrode 55. As illustrated in FIG. 24, the contact hole 56 is preferably formed within the region of the interlayer insulating film 68 located on the upper storage capacitor electrode 55a formed on a pattern forming the storage capacitor (common) line 57. The reason for this is that if the contact hole 56 is formed within the above-mentioned region, this prevents a reduction in the aperture ratio from being further caused.
For the storage capacitor element of the AM substrate illustrated in FIGS. 24 and 25, when conductive foreign particles (dust or particles) or a pin hole 99 exist in a part of the gate insulating film 63 between the storage capacitor line (lower storage capacitor electrode) 57 and the upper storage capacitor electrode 55a, this causes a short circuit between the storage capacitor line (lower storage capacitor electrode) 57 and the upper storage capacitor electrode 55a. Thus, the pixel in which a short circuit has occurred is found as a point defect on a display image. This should be improved. Furthermore, also when poor etching or poor photolithography cause a short circuit between the data signal line 53 and the upper storage capacitor electrode 55a which are formed in the same process step due to defects, such as an unnecessarily left part 98 of a film, a point defect likewise occurs and cannot be repaired. This should be devised.
For example, a liquid crystal display panel using vertically alignment (VA) liquid crystal, such as a multi-domain vertical alignment (MVA) liquid crystal, is set such that, under the condition that no voltage is applied to a liquid crystal, an associated pixel is displayed in black. In a case where a short circuit is caused between the data signal line 53 and the upper storage capacitor electrode 55a, a data signal is fed to the pixel electrode 51 without passing through the TFT 54. This prevents the data signal fed to the pixel electrode 51 from being able to be controlled by a scanning signal. In view of the above, the pixel is not displayed in black even on the condition that no voltage is applied to the liquid crystal but recognized as a bright dot. The bright dot generated when the whole area of the panel is displayed in black is more conspicuous than a black dot or a dark dot generated when the whole area thereof is displayed in white. As a result, the display quality is significantly affected by the bright dot. Techniques for repairing such point defects are disclosed in, for example, Patent Documents 3 through 5.
In recent years, pixels have increased in size with an increase in the screen areas of thin television sets. Accordingly, a defective pixel has come to be large enough to be unignorable from the viewpoint of the display quality. A technique has been developed in which, in order to reduce the size of a defective pixel, the size of a point defect is decreased by dividing one pixel into a plurality of subpixels. In this technique, a pattern becomes complicated by dividing one pixel into a plurality of subpixels, resulting in the reduced aperture ratio of the pixel. For example, for a 26-inch wide extended graphics array (WXGA) display, the aperture ratio of a pixel is reduced approximately 4% through 5%.
The structure of a liquid crystal display device in which adjacent pixels share a storage capacitor line to increase the aperture ratio of each pixel is disclosed in, for example, Patent Documents 6 and 7. More specifically, even when a pixel is divided into, for example, two subpixels, the existence of conductive foreign particles or a pin hole in a part of an insulating layer between a storage capacitor line (lower storage capacitor electrode) and an upper storage capacitor electrode causes a short circuit therebetween. The subpixel in which a short circuit occurs is recognized as a point defect on a display image. However, as compared with a case where a pixel is not divided, the area of the point defect is reduced to half. As a result, the display quality is insignificantly affected by the point defect.
FIG. 26 is a plan view schematically illustrating the configuration of a portion of an AM substrate corresponding to a pixel divided into a plurality of subpixels. FIG. 27 is a schematic cross-sectional view of the AM substrate taken along the line B-B′ in FIG. 26. In FIGS. 26 and 27, the same components as those illustrated in FIGS. 24 and 25 are denoted by the same reference numerals.
As illustrated in FIGS. 26 and 27, a pixel electrode 51 is divided into two subpixel electrodes 51L and 51R. A scanning signal line 52 for supplying scanning signals is located in the vicinity of the border between these subpixel electrodes 51L and 51R, and a data signal line 53 for supplying data signals extends along the lateral edges of the pixel electrode 51. TFTs 54L and 54R serving as switching elements are located at the intersection of the scanning signal line 52 and the data signal line 53 so as to be connected to the subpixel electrodes 51L and 51R. The scanning signal line 52 is interposed between the TFTs 54L and 54R when viewed in plan. The scanning signal line 52 is connected to gate electrodes 62L and 62R of the TFTs 54L and 54R. The drive of the TFTs 54L and 54R is controlled by scanning signals fed to the gate electrodes 62L and 62R. Furthermore, the data signal line 53 is connected to source electrodes 66a of the TFTs 54L and 54R, and thus data signals are fed to the source electrodes of the TFTs 54L and 54R. Moreover, drain electrodes 66b are connected through connection electrodes 55L and 55R to respective ones (upper storage capacitor electrodes) 55La and 55Ra of electrodes of storage capacitor elements and further connected via contact holes 56L and 56R formed in an interlayer insulating film 68 to the subpixel electrodes 51L and 51R. A storage capacitor (common) line 57 is formed on a transparent insulating substrate (insulating substrate) 61 and functions as the other electrodes (lower storage capacitor electrodes) of the storage capacitor elements. In other words, the respective upper storage capacitor electrodes 55La and 55Ra of adjacent pixels share the storage capacitor (common) line 57 as the other electrodes (lower storage capacitor electrodes) of the storage capacitor elements. The AM substrate illustrated in FIGS. 26 and 27 can be fabricated through the similar process steps to those through which the AM substrate illustrated in FIGS. 24 and 25 are fabricated.
For the AM substrate illustrated in FIGS. 26 and 27, the storage capacitor (common) line 57 is formed in the vicinity of the border between adjacent pixels to suppress a reduction in the aperture ratio of each pixel. In order to ensure sufficient storage capacity, the areas of the upper storage capacitor electrodes 55La and 55Ra opposed to the storage capacitor (common) line 57 need to be as large as possible. In view of the above, since the respective upper storage capacitor electrodes 55La and 55Ra of adjacent pixels are close to each other, it is likely to cause current leakage failures between the upper storage capacitor electrodes 55La and 55Ra adjacent to each other.
In a case where a current leakage failure is caused, two subpixel electrodes 51L and 51R sharing a storage capacitor (common) line 57 become electrically continuous, resulting in combined defects. In order to avoid this, a repair needs to be made to defects to prevent a data signal for an adjacent pixel from being fed to the pixel. For example, in order to prevent a data signal from entering from an upper storage capacitor electrode 55La of one (first pixel) of adjacent pixels into a subpixel electrode 51R of a second pixel adjacent to the first pixel, a part of the subpixel electrode 51R of the second pixel located in a contact hole 56R is removed. In this manner, the subpixel electrode 51R is electrically isolated from the upper storage capacitor electrode 55Ra. Furthermore, in order to prevent a data signal from entering through a drain electrode 66b of the second pixel and the upper storage capacitor electrodes 55La and 55Ra into a subpixel electrode 51L of the first pixel, a connection electrode 55R of the second pixel is electrically isolated from the upper storage capacitor electrode 55Ra. In view of the above, a subpixel of one (second pixel) of the adjacent pixels is nonenergized, leading to a point defect.
In other words, for an AM substrate in which a pixel is divided into a plurality of subpixels, a point defect less significantly affects the display quality than for an AM substrate in which a pixel is not divided. The AM substrate in which a pixel is divided into a plurality of subpixels may cause a current leakage failure between adjacent upper storage capacitor electrodes 55La and 55Ra, resulting in an increase in the possibility of bringing about a point defect. This should be improved.
Patent Document 1: Japanese Unexamined Patent Application Publication No. 6-95157 (page 1)
Patent Document 2: Japanese Unexamined Patent Application Publication No. 9-152625 (pages 8 through 11 and 19, FIGS. 3 and 4)
Patent Document 3: Japanese Unexamined Patent Application Publication No. 1-303415
Patent Document 4: Japanese Unexamined Patent Application Publication No. 9-222615
Patent Document 5: Japanese Unexamined Patent Application Publication No. 7-270824
Patent Document 6: Japanese Unexamined Patent Application Publication No. 2004-62146
Patent Document 7: Japanese Unexamined Patent Application Publication No. 2004-78157